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APW7190
5V or 12V Single Output PWM Controller with PFM
Features
* * * * * *
Operating with Single 5~12V Supply Voltage or Two Supply Voltages 0.6% 0.5V Reference - Over Line, Load Regulation, and Operating Temp. Drive Dual Low Cost N-Channel MOSFETs - Adaptive Shoot-Through Protection Power-On-Reset Monitoring on VCC Pin High Efficiency at Light Load Constant-On-Time Control Scheme - Switching Frequency Compensation for PWM Operation
General Description
The APW7190 is a single-phase, constant-on-time, synchronous PWM controller, which drives N-channel MOSFETs. The APW7190 allows wide input voltage that is either a single 5~12V or two supply voltage(s) for various applications. An internal 0.5V temperature-compensated reference voltage with high accuracy is designed to meet the requirement of low output voltage applications. The PWM controller operates fixed 300kHz pseudo-constant frequency PWM with an adaptive constant-on-time control. The device provides excellent transient response and accurate DC voltage output in either PFM or PWM Mode. In Pulse Frequency Mode (PFM), the APW7190 provides very high efficiency over light to heavy loads with loading-modulated switching frequencies. The device works in ultrasonic mode with PFM at no load. The unique ultrasonic mode maintains the switching frequency above 20kHz, which eliminates noise in audio applications. The APW7190 is equipped with accurate current-limit, output under-voltage, and output over-voltage protections. A Power-On-Reset function monitors the voltage on VCC to prevent wrong operation during power-on. The APW7190 has a 4ms digital soft-start to ramp up the output voltage with programmable slew rate to reduce the start-up current. A soft-stop function actively discharges the output capacitors with controlled reverse inductor current. The APW7190 is available in TDFN3x3-10 package.
* * * * * * * *
300kHz Constant Switching Frequency Integrated MOSFET Drivers and Bootstrap Diode Internal Integrated Soft-Start Built-In Ultrasonic Mode Control Scheme with PFM Adaptive Dead-Time Control Power Good Monitoring 70% Under-Voltage Protection 125% Pre-Over-Voltage and Over-Voltage Protection
* * * *
Adjustable Current-Limit Protection - Using Low-Side MOSFET' RDS(ON) s Over-Temperature Protection 3mmx3mm TDFN-10 (TDFN3x3-10) Package Lead Free and Green Devices Available (RoHS Compliant)
Applications
* * *
Mother Board Low Cost PC 5V or 12V-Input DC/DC Regulators
ANPEC reserves the right to make changes to improve reliability or manufacturability without notice, and advise customers to obtain the latest version of relevant information to verify before placing orders. Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Mar., 2009 1 www.anpec.com.tw
APW7190
Simplified Application Circuit
VCC=5Vor 12V EN/EXTREF UGATE POK PHASE LGATE/OCSET ROCSET APW7190 Q2 COUT Q1 LOUT VOUT VIN
Pin Configuration
BOOT 1 UGATE 2 PHASE 3 GND 4 LGATE/OCSET 5 TDFN3x3-10 Top View 10 9 8 7 6 EN/EXTREF POK VOUT FB VCC
= Thermal Pad (connected to the GND plane for better heat dissipation)
Ordering and Marking Information
APW7190 Assembly Material Handling Code Temperature Range Package Code APW 7190 XXXXX Package Code QB : TDFN3x3-10 Temperature Range I : -40 to 85 C Handling Code TR : Tape & Reel Assembly Material G : Halogen and Lead Free Device
APW7190 QB :
XXXXX - Date Code
Note: ANPEC lead-free products contain molding compounds/die attach materials and 100% matte tin plate termination finish; which are fully compliant with RoHS. ANPEC lead-free products meet or exceed the lead-free requirements of IPC/JEDEC J-STD-020C for MSL classification at lead-free peak reflow temperature. ANPEC defines "Green" to mean lead-free (RoHS compliant) and halogen free (Br or Cl does not exceed 900ppm by weight in homogeneous material and total of Br and Cl does not exceed 1500ppm by weight).
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APW7190
Absolute Maximum Ratings
Symbol VCC VBOOT-GND VBOOT VCC Supply Voltage (VCC to GND) BOOT Supply Voltage (BOOT to GND ) BOOT Supply Voltage (BOOT to PHASE) FB, EN/EXTREF and VOUT to GND POK to GND UGATE Voltage (UGATE to PHASE) <400ns pulse width >400ns pulse width LGATE/OCSET Voltage (LGATE to GND) <400ns pulse width >400ns pulse width VPHASE TJ TSTG TSDR PHASE Voltage (PHASE to GND) <400ns pulse width >400ns pulse width Maximum Junction Temperature Storage Temperature Maximum Lead Soldering Temperature, 10 Seconds
(Note 1)
Rating -0.3 ~ 16 -0.3 ~ 30 -0.3 ~ 16 -0.3 ~ 7 -0.3 ~ VCC+0.3 -5 ~ VBOOT+0.3 -0.3 ~ VBOOT+0.3 -5 ~ VCC+0.3 -0.3 ~ VCC+0.3 -10 ~ 30 -0.3 ~ 16 150 -65 ~ 150 260 Unit V V V V V V
Parameter
V
V
o o o
C C
C
Note 1 : Absolute Maximum Ratings are those values beyond which the life of a device may be impaired. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Thermal Characteristics
Symbol JA JC Parameter Thermal Resistance -Junction to Ambient Thermal Resistance -Junction to Case
(Note 2)
Typical Value TDFN3x3-10 55 5
Unit C/W C/W
(Note 3)
TDFN3x3-10
Note 2 : JA is measured with the component mounted on a high effective the thermal conductivity test board in free air. The exposed pad of package is soldered directly on the PCB. Note 3 : The case temperature is measured at the center of the exposed pad on the underside of the TDFN3x3-10 package.
Recommended Operating Conditions (Note 4)
Symbol VIN VCC VOUT IOUT TA TJ Converter Input Voltage VCC, PVCC Supply Voltage Converter Output Voltage Converter Output Current Ambient Temperature Junction Temperature Parameter Range 2.2 ~ 13.2 4.5 ~ 13.2 0.5 ~ 3.3 0 ~ 40 -40 ~ 85 -40 ~ 125 Unit V V V A
o o
C
C
Note 4 : Refer to the typical application circuit.
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APW7190
Electrical Characteristics
These specifications apply for TA = -40C to +85C, unless otherwise stated. All typical specifications TA= +25C, VIN= 12V, VCC = 12V.
Symbol SUPPLY CURRENT IVCC-PWM IVCC-PFM IVCC_SHDN
Parameter
Test Conditions Min.
APW7190 Typ. Max.
Unit
VCC Input Bias Current at PWM Mode VCC Input Bias Current at PFM Mode VCC Shutdown Current
UGATE and LGATE Open UGATE and LGATE Open
-
1.7 350 -
2.5 550 70
mA A A
FEEDBACK VOLTAGE VREF Reference Voltage Regulation Accuracy Line and Load Regulation IFB FB Input Bias Current TA = -40 C ~ 85 C 0A < IOUT < 40A; 4V < VCC < 13.2V VFB=0.5V
o o
-0.6 -0.2 -0.5
0.5 -
+0.6 +0.2 +0.5
V % % A
PWM CONTROLLERS TON(MIN) TOFF(MIN) TSS Minimum on Time of UGATE Minimum off Time of UGATE Internal Soft-Start Time Zero Crossing Voltage Threshold PWM to PFM Debounce Time PFM to PWM Debounce Time PFM/PWM On Time Ratio GATE DRIVER UGATE Source Resistance UGATE Sink Resistance LGATE Source Resistance LGATE Sink Resistance UGATE Source Resistance UGATE Sink Resistance LGATE Source Resistance LGATE Sink Resistance Dead Time VCC POWER-ON-RESET (POR) THRESHOLD VVCC_THR Rising VCC POR Threshold Voltage VCC POR Hysteresis OSCILLATOR FSW Switching Frequency in PWM Mode Minimum Ultrasonic Operating Frequency DC Output Current, VCC=4.5V~13.2V VCC=4.5V ~ 13.2V 270 20 300 25 330 kHz kHz 3.9 0.1 4.1 0.2 4.3 0.3 V V VBOOT=12V, ISOURCE=100mA VBOOT=12V, ISINK=100mA VCC=12V, ISOURCE=100mA VCC=12V, ISINK=100mA VBOOT=5V, ISOURCE=100mA VBOOT=5V, ISINK=100mA VCC=5V, ISOURCE=100mA VCC=5V, ISINK=100mA
(Note 5)
Over Temperature and VCC Over Temperature and VCC From VFB=0V to POK Rises Up
3 -3 -
100 350 4 0 20 20 1.2
5 +3 -
ns ns ms mV s s
PFM On Time / PWM On Time
-
20
1.8 2.2 1.2 1.4 2.4 3 1.8 1.8 25
2.7 3.3 1.8 2.1 3.75 4.5 2.7 2.7 60
ns
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APW7190
Electrical Characteristics (Cont.)
These specifications apply for TA = -40C to +85C, unless otherwise stated. All typical specifications TA= +25C, VIN= 12V, VCC = 12V.
Symbol CONTROL INPUTS
Parameter
Test Conditions Min.
APW7190 Typ. Max.
Unit
Shutdown Threshold, EN/EXTREF Falling EN/EXTREF Input Voltage External Reference, VOUT=VEN/EXTREF PWM on Logic High Threshold, EN/EXTREF Rising EN/EXTREF Leakage Current POWER OK INDICATOR (POK) VFB is from low to target value (POK Goes High) VPOK POK Threshold ~3s noise filter, VFB Falling (POK Goes Low) ~3s noise filter, VFB Rising (POK Goes Low) IPOK VPOK PROTECTION IOCSET VOCSET_MAX VUV IOCSET Source Current Built-in Maximum Current-Limit Threshold Voltage Under-Voltage Protection Threshold Under-Voltage Protection Debounce Interval VOVR Over-Voltage Protection Rising Threshold Over-Voltage Protection Falling Threshold Over-Voltage Protection Debounce Interval TOTR Over-Temperature Protection Rising Threshold (Note 5) Over-Temperature Protection Hysteresis (Note 5)
Note 5 : Guaranteed by design.
0.5 3.5 -0.1
-
0.4 3.3 0.1
V V V A
VEN/EXTREF=0V
93 65 120 -
95 70 125 0.1 0.5
97 75 130 1.0 1
% % % A V
POK Leakage Current POK Output Low Voltage
VPOK=5V IPOK=-4mA
IOCSET Sourcing
9 230 65 120 100 -
10 250 70 2 125 105 2 150 20 -
11 270 75 130 110 -
A mV % s % % s
o
C C
o
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APW7190
Typical Operating Characteristics
Referece Voltage vs. Output Current
0.503 Reference Voltage,VREF (V) 0.502
Efficiency (%) 100 90 80 70 60 50 40 30 20 10
H-Side:IPD090N03LGx1, L-Side:IPD060N03LGx2 H-Side:IPD090N03LGx2, L-Side:IPD060N03LGx2 H-Side:BSC090N03LSGx1, L-Side:NTMFS4839NH-Dx2 H-Side:BSC090N03LSGx2, 1 1 L-Side:NTMFS4839NH-Dx2 0
Efficiency vs. Output Current
VIN=12V, VCC=12V, L=1H,VOUT=1.1V
0.501 0.5 0.499 0.498 0.497 -40
-20
0
20
40
60 (oC
80 )
100
0 0.1
1
10
100
Junction Temperature,T J
Output Current,I OUT (A)
Switching Frequnecy vs. Input Voltage
330 Switching Frequency, FSW (kHz)
Switching Frequnecy vs. Output Current
350 Switching Frequency, FSW (kHz) 300 250 200 150 100 50 0 0 5 10 15 20 25 30 Outupt Current,I OUT (A) 35 40
320 310 300 290 280 270
2
4
6
8
10
12
Input Voltage,VIN (V)
Switching Frequency Over Temperature
330 Switching Frequency, FSW (kHz) 320 310 300 290 280 270 -40
-20
0
20
40
60 (oC)
80
100
Junction Temperature,T J
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APW7190
Operating Waveforms
Enable at Zero Initial Voltage of VOUT Enable before End of Soft-Stop
VEN/EXTREF 1 1
VEN/EXTREF VOUT
VOUT 2 VPHASE 3 VPOK 4 4 2 VPHASE 3 VPOK
CH1: VEN/EXTREF (5V/div) CH2: VOUT (1V/div) CH3: VPHASE (10V/div) CH4: VPOK (10V/div) Time: 5ms/div
CH1: VEN/EXTREF (5V/div) CH2: VOUT (1V/div) CH3: VPHASE (10V/div) CH4: VPOK (10V/div) Time: 10ms/div
Shutdown at IOUT=20A
VEN/EXTREF 1
Shutdown with Soft-Stop at No Load
VEN/EXTREF 1
VOUT VPHASE
VOUT VPHASE
2 3
2 3
VPOK 4
4
VPOK
CH1: VEN/EXTREF (5V/div) CH2: VOUT (1V/div) CH3: VPHASE (10V/div) CH4: VPOK (10V/div) Time: 20s/div
CH1: VEN/EXTREF (5V/div) CH2: VOUT (1V/div) CH3: VPHASE (10V/div) CH4: VPOK (10V/div) Time: 50ms/div
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APW7190
Operating Waveforms (Cont.)
Mode Change (External Mode <=> Internal Mode) Mode Transient of PWM to PFM
VEN/EXTREF
VEN/EXTREF 1 VOUT 1 VOUT 2 2
CH1: VEN/EXTREF (1V/div) CH2: VOUT (1V/div) Time: 10ms/div
CH1: VEN/EXTREF (1V/div) CH2: VOUT (1V/div) Time: 20ms/div
Load Transient 0A->10A
Load Transient 10A->0A
VPHASE
VPHASE 1 1 VLGATE VLGATE VOUT 2 3 VOUT
2 3
IL 4 4
IL
CH1: VPHASE (10V/div) CH2: VLGATE (10V/div) CH3: VOUT (AC, 50mV/div) CH4: IL (10A/div) Time: 10s/div
CH1: VPHASE (10V/div) CH2: VLGATE (10V/div) CH3: VOUT (AC, 50mV/div) CH4: IL (10A/div) Time: 10s/div
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APW7190
Operating Waveforms (Cont.)
Current-Limit and UV Protections
VPHASE VLGATE 2
Short Circuit Test
VPHASE 1 2 VLGATE
1
VOUT VOUT 3 3
IL 4
4
IL
CH1: VPHASE (20V/div) CH2: VLGATE (20V/div) CH3: VOUT (500mV/div) CH4: IL (10A/div) Time: 200s/div
CH1: VPHASE (20V/div) CH2: VLGATE (20V/div) CH3: VOUT (500mV/div) CH4: IL (10A/div) Time: 10s/div
Operating at UTRASONIC Mode
Operating at PFM Mode
VPHASE 1 VLGATE 2 3 VOUT
VPHASE 1
2 3
IL
VLGATE VOUT
IL 4
4
CH1: VPHASE (10V/div) CH2: VLGATE (10V/div) CH3: VOUT (AC,50mV/div) CH4: IL (5A/div) Time: 10s/div
CH1: VPHASE (10V/div) CH2: VLGATE (10V/div) CH3: VOUT (AC,50mV/div) CH4: IL (5A/div) Time: 2s/div
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APW7190
Operating Waveforms (Cont.)
Operating at PWM Mode
VPHASE 1
2 3
VLGATE
VOUT 4 IL
CH1: VPHASE (10V/div) CH2: VLGATE (10V/div) CH3: VOUT (AC,50mV/div) CH4: IL (5A/div) Time: 2s/div
Pin Description
PIN NO. 1 NAME BOOT This pin provides ground referenced bias voltage to the high-side MOSFET driver. A bootstrap circuit with a diode connected to 5~12V is used to create a voltage suitable to drive a logic-level N-channel MOSFET. Connect this pin to the high-side N-channel MOSFET' gate. This pin provides gate drive for the s high-side MOSFET. The pin provides return path for the high-side MOSFET driver' pull-low current. Connect this pin s to the high-side MOSFET' source. s The GND terminal provides return path for the IC' bias current and the low-side MOSFET s driver' pull-low current. Connect the pin to the system ground via very low impedance layout on s PCBs. FUNCTION
2 3
UGATE PHASE
4
GND
5
Low-side Gate Driver Output and Over-Current Setting Input. This pin is the gate driver for LGATE/OCSET low-side MOSFET. It also used to set the maximum inductor current. Refer to the section in "Function Description" for detail. VCC Connect this pin to a 5~12V supply voltage. This pin provides bias supply for the control circuitry and the low-side MOSFET driver. The voltage at this pin is monitored for the Power-On-Reset (POR) purpose. Output Voltage Feedback pin. This pin is connected to the resistive divider that set the desired output voltage. The PGOOD, UVP, and OVP circuits detect this signal to report output voltage status. The VOUT pin makes a direct measurement of the converter output voltage. The VOUT pin should be connected to the top feedback resistor at the converter output. POK is an open drain output used to indicate the status of the output voltage. Connect the POK pin to +5V or +12V through a pull-high resistor. Enable/Shutdown Pin or External Reference Selection of The PWM Controller.
6
7
FB
8 9 10
VOUT POK EN/EXTREF
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APW7190
Block Diagram
POK
VOUT VOUT Sense Low-Side GND
VREF x 125%
Debounce Time
VOCSET
VREF x 95% /70% 125% VREF OV 300kHz Fault Latch Logic UV 70% VREF FB On-Time Generator Error Comparator PWM Signal Controller Thermal Shutdown Ocillator
Current-Limit
BOOT
UGATE
PHASE
ZC
VCC
VCC VREF VCC VOUT POR
Digital Soft-Start LGATE/OCSET Sample and Hold PHASE 10A
EN/EXTREF
VOCSET
To LGATE/OCSET
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APW7190
Typical Application Circuit
APW7190
VPOK
POK CIN UGATE RPOK 10K BOOT CBOOT PHASE 0.1F LOUT 1H Q1 APM4350
VIN 2.2V ~ 13.2V
820F x 2
5VBUS
12V
VOUT COUT 820F x 3
RVCC
2.2 VCC
LGATE/OCSET ROCSET 15K, 1%
Q2 APM4354 RTOP
CVCC
1F GND VOUT
CFB-VOUT 10nF
1.1K,1%
FB 5V EN/EXTREF RGND 1K, 1%
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APW7190
Function Description
Constant-On-Time PWM Controller with Input FeedForward The constant-on-time control architecture is a pseudofixed frequency with input voltage feed-forward. This architecture relies on the output filter capacitor' effective s series resistance (ESR) to act as a current-sense resistor, so the output ripple voltage provides the PWM ramp signal. In PFM operation, the high-side switch on-time controlled by the on-time generator is determined solely by a oneshot whose pulse width is inversely proportional to input voltage and directly proportional to output voltage. In PWM operation, the high-side switch on-time is determined by a switching frequency control circuit in the on-time generator block. The switching frequency control circuit senses the switching frequency of the high-side switch and keeps regulating it at a constant frequency in PWM mode. The design improves the frequency variation and is more outstanding than a conventional constant-ontime controller, which has large switching frequency variation over input voltage, output current, and temperature. Both in PFM and PWM, the on-time generator, which senses input voltage on PHASE pin, provides a very fast on-time response to input line transients. Another one-shot sets a minimum off-time (typical: 350ns). The on-time one-shot is triggered if the error comparator is high, the low-side switch current is below the current-limit threshold, and the minimum off-time oneshot has timed out. Pulse-Frequency Modulation (PFM) In PFM mode, an automatic switchover to pulse-frequency modulation (PFM) takes place at light loads. This switchover is affected by a comparator that truncates the low-side switch on-time at the inductor current zero crossing. This mechanism causes the threshold between PFM and PWM operation to coincide with the boundary between continuous and discontinuous inductor-current operation (also known as the critical conduction point). The on-time of PFM mode is designed at 1.2 time of the nominal on-time of PWM mode. The on-time of PFM is given by: This design provides a hysteresis of converter output current to prevent wrong or repeatedly PFM/PWM handoff with constant output current. The load current at handoff from PFM to PWM mode is given by:
ILOAD(PFM to PWM) = 1 VIN - VOUT x xTON - PFM 2 L VIN - VOUT 1.2 VOUT = x x 2L FSW VIN
The load current at handoff from PWM to PFM mode is given by:
ILOAD(PWM to PFM) = = 1 2 L VIN - VOUT 2L x VIN - VOUT xTON - PWM x VOUT VIN
x
1 FSW
Therefore, the ILOAD(PFM to PWM) is 1.2 time of the ILOAD(PWM to PFM). In this case, APW7190 operates in ultrasonic mode with PFM when the load is zero. The ultrasonic mode is illustrated as below description. Ultrasonic Mode The ultrasonic mode activates an unique PFM mode with a minimum switching frequency of 20kHz. The minimum frequency 20kHz of ultrasonic mode eliminates audiofrequency interference in light load condition. It will transit to an unique PFM mode when output loading makes the frequency bigger than ultrasonic frequency. In ultrasonic mode, the controller automatically transits to fixed-frequency PWM operation when the load reaches the same critical conduction point (ILOAD(PFM to PWM)). When the controller detects that no switching has occurred within about 40s (Typical), an ultrasonic pulse will be occurred. The ultrasonic controller turns on the low-side MOSFET firstly to reduce the output voltage. After feedback voltage drops below the internal reference voltage, the controller turns off the low-side MOSFET and triggers a constant-on-time. When the constant-on-time has expired, the controller turns on the low-side MOSFET again until the inductor current is below the zero-crossing threshold. The behavior is the same as PFM mode.
TON-PFM =
1.2 VOUT x FSW VIN
Where FSW is the nominal switching frequency of the converter in PWM mode.
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APW7190
Function Description (Cont.)
V
Power-On-Reset (POR) A Power-On-Reset (POR) function is designed to prevent wrong logic controls when the VCC voltage is low. The POR function continually monitors the bias supply voltage on the VCC pin if at least one of the enable pins is set high. When the rising VCC voltage reaches the rising POR voltage threshold (4.1V, typical), the POR signal goes high and the chip initiates soft-start operations. When this voltage drop lower than 3.9V (typical), the POR disables the chip. EN/EXTREF Pin Control The voltage (V EN/EXTREF) applied to EN/EXTREF pin selects either enable-shutdown or adjustable external reference. When VEN/EXTREF is above the EN high threshold (3.5V, typical), the PWM is enabled. When VEN/EXTREF is from 0.5V to 3.3V, the output voltage can be programmed as same as VEN/EXTREF voltage. When VEN/EXTREF is below the EN low threshold (0.4V, typical), the chip is in the shutdown and only low leakage current is taken from VCC. Digital Soft-Start The APW7190 integrates digital soft-start circuits to ramp up the output voltage of the converter to the programmed regulation setpoint at a predictable slew rate. The slew rate of output voltage is internally controlled to limit the inrush current through the output capacitors during softstart process. The figure 1 shows soft-start sequence. When the EN/EXTREF pin is pulled above the rising EN threshold voltage, the VOCSET voltage is equal to 10A x ROCSET. When VCC rising POR threshold is triggered, the device starts to sample and hold the current-limit setting threshold. The sample time is as below: IOCSET(A) x ROCSET(k) x 5 x 10-3 sec. When current-limit setting action has finished, the device initiates a soft-start process to ramp up the output voltage. The soft-start interval, TSS, is about 4ms (typical value).
t0
TSS = t2-t1 = 4ms VCC VPOK 95% x VREF VOUT EN
t1
t2
t
Figure 1. Soft-Start Sequence During soft-start stage before the POK pin is ready, the under-voltage protection is prohibited. The over-voltage and over-current protection functions are enabled. If the output capacitor has residue voltage before startup, both low-side and high-side MOSFETs are in off-state until the internal digital soft start voltage equal the VFB voltage. This will ensure the output voltage starts from its existing voltage level. In the event of under-voltage, over-voltage, over-temperature or shutdown, the chip enables the soft-stop function. The soft-stop function discharges the output voltage to GND through an internal 20 switch. Cycling the EN/ EXTREF enable signal or VCC power-on-reset signal can reset the latch. Power OK Indicator The APW7190 features an open-drain POK pin to indicate output regulation status. In normal operation,when the output voltage rises 95% of its target value, the POK goes high. When the output voltage outruns 70% or 125% of the target voltage, POK signal will be pulled low immediately. Since the FB pin is used for both feedback and monitoring purposes, the output voltage deviation can be coupled directly to the FB pin by the capacitor in parallel with the voltage divider as shown in the typical applications. In order to prevent false POK drop, capacitors need to parallel at the output to confine the voltage deviation with severe load step transient and the POK comparator has a built-in 3s noise filter.
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APW7190
Function Description (Cont.)
Under-Voltage Protection (UVP) In the process of operation, if a short-circuit occurs, the output voltage will drop quickly. When the load current is bigger than current-limit threshold value, the output voltage will fall out of the required regulation range. The under-voltage protection circuit continually monitors the VFB after soft-start is completed. If a load step is strong enough to pull the output voltage lower than the under-voltage threshold, the device starts to soft-stop process to shut down the output gradually. The under-voltage threshold is 70% of the normal output voltage. The under-voltage comparator has a built-in 2s noise filter to prevent the chip from wrong UVP shutdown caused by noise. Cycling the EN/EXTREF enable signal or VCC power-onreset signal can reset the latch. Over-Voltage Protection (OVP) The over-voltage function monitors the output voltage by FB pin. When the FB voltage increases over 125% of the reference voltage due to the high-side MOSFET failure or for other reasons, the over-voltage protection comparator designed with a 2s noise filter will force the low-side MOSFET gate driver fully turn on. This action actively pulls down the output voltage. When the FB voltage decreases below 105%, the OVP comparator is disengaged and both high-side and low-side drivers turn off. This OVP scheme only clamps the voltage overshoot and does not invert the output voltage when otherwise activated with a continuously high output from low-side MOSFET driver. It' a common problem for OVP schemes s with a latch. Once an over-voltage fault condition is set, it can only be reset by toggling EN/EXTREF enable signal or VCC power-on-reset signal. Current-Limit The current-limit circuit employs a "valley" current-sensing algorithm (See Figure 2). The APW7190 uses the low-side MOSFET RDS(ON) of the synchronous rectifier as a current-sensing element. If the magnitude of the current-sense signal at PHASE pin is above the current-limit threshold, the PWM is not allowed to initiate a new cycle. The actual peak current is greater than the current-limit threshold by an amount equal to the inductor ripple current. Therefore, the exact current-limit characteristic and maximum load capability are the functions of the sense resistance, inductor value, and input voltage.
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INDUCTOR CURRENT IPEAK
IOUT
G
I
ILIMIT
0
Time
Figure 2. Current-Limit Algorithm A resistor (ROCSET), connected from the LGATE/OCSET to GND, programs the current-limit threshold. Before the IC initiates a soft-start process, an internal current source, IOCSET (10A typical), flowing through the ROCSET develops a voltage (VOCSET) across the ROCSET. The device holds VOCSET and stops the current source, IOCSET, during normal operation. The relationship between the sampled voltage VOCSET and the current-limit threshold ILIMIT is given by: 10A x ROCSET = ILIMIT x RDS(ON) ILIMIT can be expressed as IOUT minus half of peak-to-peak inductor current. The APW7190 has an internal current-limit voltage (VOCSET_MAX), and the value is 0.25V typical. When the R OCSET x IOCSET exceeds 0.25V or the ROCSET is floating or not connected, the over current threshold will be the internal default value 0.25V. The PCB layout guidelines should ensure that noise and DC errors do not corrupt the current-sense signals at PHASE. Place the hottest power MOSEFTs as close to the IC as possible for best thermal coupling. When combined with the under-voltage protection circuit, this current-limit method is effective in almost every circumstance. Over-Temperature Protection (OTP) When the junction temperature increases above the rising threshold temperature TOTR , the IC will enter the overtemperature protection state that suspends the PWM, which forces the UGATE and LGATE gate drivers output low. The thermal sensor allows the converters to start a start-up process and regulate the output voltage again after the junction temperature cools by 20oC. The OTP is designed with a 20oC hysteresis to lower the average TJ during continuous thermal overload conditions, which increases lifetime of the APW7190.
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APW7190
Application Information
Output Voltage Setting The output voltage is adjustable from 0.5V to 3.3V with a resistor-divider connected with FB, GND, and converter' s output or the voltage (VEN/EXTREF) applied to EN/EXTREF pin selects adjustable external reference. Using 1% or better resistors for the resistor-divider is recommended. The output voltage is determined by:
R VOUT = 0.5 x 1 + TOP R GND
choose the ripple current to be approximately 30% of the maximum output current. Once the inductance value has been chosen, selecting an inductor which is capable of carrying the required peak current without going into saturation. In some types of inductors, especially core that is made of ferrite, the ripple current will increase abruptly when it saturates. This results in a larger output ripple voltage. Besides, the inductor needs to have low DCR to reduce the loss of efficiency. Output Capacitor Selection Output voltage ripple, the transient voltage deviation and the stability issue are factors which have to be taken into consideration when selecting an output capacitor. Higher capacitor value and lower ESR reduce the output ripple and the load transient drop. Generally, selecting high performance low ESR capacitors is recommended for switching regulator applications. In addition to high frequency noise related to MOSFET turn-on and turn-off, the output voltage ripple includes the capacitance voltage drop VCOUT and ESR voltage drop VESR caused by the AC peak-to-peak inductor' current. These two voltages can s be represented by: VCOUT = VESR IRIPPLE 8COUTFSW = IRIPPLE x RESR
Where 0.5 is the reference voltage, RTOP is the resistor connected from converter' output to FB, and RGND is the s resistor connected from FB to GND. Suggested RGND is in the range from 1K to 20k. To prevent stray pickup, locate resistors RTOP and RGND close to APW7190. Similarly, when VEN/EXTREF is from 0.5V to 3.3V, the output voltage can be programmed as same as VEN/EXTREF voltage. Output Inductor Selection The duty cycle (D) of a buck converter is the function of the input voltage and output voltage. Once an output voltage is fixed, it can be written as: D= VOUT VIN
The inductor value (L) determines the inductor ripple current, IRIPPLE, and affects the load transient response. Higher inductor value reduces the inductor' ripple curs rent and induces lower output ripple voltage. The ripple current and ripple voltage can be approximated by:
IRIPPLE = VIN - VOUT VOUT x FSW x L VIN
These two components constitute a large portion of the total output voltage ripple. In some applications, multiple capacitors have to be paralleled to achieve the desired ESR value. If the output of the converter has to support another load with high pulsating current, more capacitors are needed in order to reduce the equivalent ESR and suppress the voltage ripple to a tolerable level. Nevertheless, the constant-on-time (COT) control architecture relies on the output capacitor' ESR to act as a s current-sense resistor, so the output ripple voltage provides the PWM ramp signal. For stability issue, the output ripple also need to be considered. By stability experimentation result, suggesting the feedback ripple is about 25mV to 50mV. To support a load transient that is faster than the switching frequency, more capacitors are needed for reducing the voltage excursion during load step change. Another
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Where FSW is the switching frequency of the regulator. Although the inductor value and frequency are increased and the ripple current and voltage are reduced, a tradeoff exists between the inductor' ripple current and the regus lator load transient response time. A smaller inductor will give the regulator a faster load transient response at the expense of higher ripple current. Increasing the switching frequency (F SW ) also reduces the ripple current and voltage, but it will increase the switching loss of the MOSFETs and the power dissipation of the converter. The maximum ripple current occurs at the maximum input voltage. A good starting point is to
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APW7190
Application Information
Output Capacitor Selection (Cont.) aspect of the capacitor selection is that the total AC current going through the capacitors has to be less than the rated RMS current specified on the capacitors in order to prevent the capacitor from over-heating. Input Capacitor Selection The input capacitor is chosen based on the voltage rating and the RMS current rating. For reliable operation, selecting the capacitor voltage rating to be at least 1.3 times higher than the maximum input voltage. The maximum RMS current rating requirement is approximately IOUT/2, where IOUT is the load current. During power-up, the input capacitors have to handle great amount of surge current. For low-duty notebook appliactions, ceramic capacitor is recommended. The capacitors must be connected between the drain of high-side MOSFET and the source of low-side MOSFET with very low-impeadance PCB layout. MOSFET Selection The selection of the N-channel power MOSFETs are determined by the R DS(ON), reversing transfer capacitance (CRSS) and maximum output current requirement. The losses in the MOSFETs have two components: conduction loss and transition loss. For the high-side and low-side MOSFETs, the losses are approximately given by the following equations: Phigh-side = IOUT 2(1+ TC)(RDS(ON))D + (0.5)( IOUT)(VIN)( tSW)FSW Plow-side = IOUT 2(1+ TC)(RDS(ON))(1-D) Where IOUT is the load current TC is the temperature dependency of RDS(ON) FSW is the switching frequency tSW is the switching interval D is the duty cycle Note that both MOSFETs have conduction losses while the high-side MOSFET includes an additional transition loss. The switching interval, tSW , is the function of the reverse transfer capacitance CRSS. The (1+TC) term is a factor in the temperature dependency of the RDS(ON) and can be extracted from the "RDS(ON) vs. Temperature" curve of the power MOSFET.
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Layout Consideration In any high switching frequency converter, a correct layout is important to ensure proper operation of the regulator. With power devices switching at higher frequency, the resulting current transient will cause voltage spike across the interconnecting impedance and parasitic circuit elements. As an example, consider the turn-off transition of the PWM MOSFET. Before turn-off condition, the MOSFET is carrying the full load current. During turn-off, current stops flowing in the MOSFET and is freewheeling by the low side MOSFET and parasitic diode. Any parasitic inductance of the circuit generates a large voltage spike during the switching interval. In general, using short and wide printed circuit traces should minimize interconnecting impedances and the magnitude of voltage spike. Besides, signal and power grounds are to be kept separating and finally combined using ground plane construction or single point grounding. Figure 3 illustrates the layout, with bold lines indicating high current paths; these traces must be short and wide. Components along the bold lines should be placed lose together. Below is a checklist for your layout: = Keep the switching nodes (UGATE, LGATE/OCSET, BOOT, and PHASE) away from sensitive small signal nodes since these nodes are fast moving signals. Therefore, keep traces to these nodes as short as possible and there should be no other weak signal traces in parallel with theses traces on any layer. = The signals going through theses traces have both high dv/dt and high di/dt with high peak charging and discharging current. The traces from the gate drivers to the MOSFETs (UGATE and LGATE/OCSET) should be short and wide. = Place the source of the high-side MOSFET and the drain of the low-side MOSFET as close as possible. Minimizing the impedance with wide layout plane between the two pads reduces the voltage bounce of the node. In addition, the large layout plane between the drain of the MOSFETs (VIN and PHASE nodes) can get better heat sinking. = Decoupling capacitors, the resistor-divider, and boot capacitor should be close to their pins. (For example, place the decoupling ceramic capacitor close to the drain of the high-side MOSFET as close as possible.)
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APW7190
Application Information (Cont.)
Layout Consideration (Cont.) = The input bulk capacitors should be close to the drain of the high-side MOSFET, and the output bulk capacitors should be close to the loads. The input capacitor' ground should be close to the grounds of the s output capacitors and low-side MOSFET. = Locate the resistor-divider close to the FB pin to minimize the high impedance trace. In addition, FB pin traces can' be close to the switching signal traces t (UGATE, LGATE/OCSET, BOOT, and PHASE). = The ROCSET resistance should be placed near the IC as close as possible.
APW7190
VIN VCC BOOT L O A D
UGATE PHASE LGATE/OCSET ROCSET Close to IC VOUT
Figure 3.
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APW7190
Package Information
TDFN3x3-10
D A
E
Pin 1
D2
A1 A3
Pin 1 Corner
e S Y M B O L A A1 A3 b D D2 E E2 e L K 0.30 0.20 0.18 2.90 2.20 2.90 1.40 0.50 BSC 0.50 0.012 0.008 TDFN3x3-10 MILLIMETERS MIN. 0.70 0.00 0.20 REF 0.30 3.10 2.70 3.10 1.75 0.007 0.114 0.087 0.114 0.055 0.020 BSC 0.020 MAX. 0.80 0.05 MIN. 0.028 0.000 0.008 REF 0.012 0.122 0.106 0.122 0.069 INCHES MAX. 0.031 0.002
Note : 1. Followed from JEDEC MO-229 VEED-5.
Copyright (c) ANPEC Electronics Corp. Rev. A.1 - Mar., 2009
19
L
E2
b
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APW7190
Carrier Tape & Reel Dimensions
P0 P2 P1
OD0
A E1 F
K0 B SECTION A-A
B0
A0
OD1 B
A
SECTION B-B
T
d
Application
A
H
H A
T1
T1
C
d
D
W
W
E1
F
178.0O .00 50 MIN. 2
TDFN3x3-10 P0 P1
8.4+2.00 13.0+0.50 0 0 -0.00 -0.20 1.5 MIN. 20.2 MIN. 8.0O .20 1.75O .10
P2 D0 D1 T A0 B0
3.5O .05 0
K0
4.0O .10 0
4.0O .10 0
2.0O .05 0
1.5+0.10 -0.00
1.5 MIN.
0.6+0.00 0 0 0 -0.40 3.35O .20 3.35O .20 1.30O .20
(mm)
Devices Per Unit
Package Type TDFN3x3-10 Unit Tape & Reel Quantity 3000
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APW7190
Taping Direction Information
TDFN3x3-10
t
USER DIRECTION OF FEED
Classification Profile
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APW7190
Classification Reflow Profiles (Cont.)
Profile Feature Preheat & Soak Temperature min (Tsmin) Temperature max (Tsmax) Time (Tsmin to Tsmax) (ts) Average ramp-up rate (Tsmax to TP) Liquidous temperature (TL) Time at liquidous (tL) Peak (Tp)* package body Temperature Sn-Pb Eutectic Assembly 100 C 150 C 60-120 seconds 3 C/second max. 183 C 60-150 seconds See Classification Temp in table 1 20** seconds 6 C/second max. 6 minutes max. Pb-Free Assembly 150 C 200 C 60-120 seconds 3C/second max. 217 C 60-150 seconds See Classification Temp in table 2 30** seconds 6 C/second max. 8 minutes max.
Time (tP)** within 5C of the specified classification temperature (Tc) Average ramp-down rate (Tp to Tsmax) Time 25C to peak temperature
* Tolerance for peak profile Temperature (Tp) is defined as a supplier minimum and a user maximum. ** Tolerance for time at peak profile temperature (tp) is defined as a supplier minimum and a user maximum. Table 1. SnPb Eutectic Process - Classification Temperatures (Tc) Package Thickness <2.5 mm 2.5 mm
3
Volume mm <350 235 C 220 C
3
Volume mm 350 220 C 220 C
3
3
Table 2. Pb-free Process - Classification Temperatures (Tc) Package Thickness <1.6 mm 1.6 mm - 2.5 mm 2.5 mm Volume mm <350 260 C 260 C 250 C Volume mm 350-2000 260 C 250 C 245 C Volume mm >2000 260 C 245 C 245 C
3
Reliability Test Program
Test item SOLDERABILITY HOLT PCT TCT ESD Latch-Up Method JESD-22, B102 JESD-22, A108 JESD-22, A102 JESD-22, A104 MIL-STD-883-3015.7 JESD 78 Description 5 Sec, 245C 1000 Hrs, Bias @ 125C 168 Hrs, 100%RH, 2atm, 121C 500 Cycles, -65C~150C VHBMU2KV, VMMU200V 10ms, 1trU 100mA
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APW7190
Customer Service
Anpec Electronics Corp. Head Office : No.6, Dusing 1st Road, SBIP, Hsin-Chu, Taiwan Tel : 886-3-5642000 Fax : 886-3-5642050 Taipei Branch : 2F, No. 11, Lane 218, Sec 2 Jhongsing Rd., Sindian City, Taipei County 23146, Taiwan Tel : 886-2-2910-3838 Fax : 886-2-2917-3838
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